Design and Performance Analysis of A Reconfigurable Arbiter

This paper presents the design and performance analysis of an arbiter with a hybrid arbitration algorithm. The hybrid arbitration algorithm contains static fixed priority algorithm in conjunction with dynamic algorithm to gain better system performance is described. The performance analysis for the various combinations of the arbitration algorithms under different traffic loads is simulated. The results indicate a better performance can be achieved as compared with the traditional arbitration assignment scheme. Based on the performance analysis, the hybrid arbitration can be custom-tuned to meet the design requirements. The implementation of the arbiter with hybrid arbitration scheme for system on chip applications is also explained. The reconfigurable arbiter was implemented by FPGA and synthesized by Synopsys Design Complier with a TSMC 0.18 m μ cell library. In addition, the power analysis of the reconfigurable arbiter at various arbitration states is reported. The reconfigurable arbiter can be custom-tuned to obtain high bandwidth utilization, low latency, and power effective for on-chip bus communication.